Data Flow Partitioning with Clock Period and Latency Constraints - Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

We propose an efficient performance-driven twoway partitioning algorithm to take into account clock period and latency with retiming. We model the problem with a Quadratic Programming formulation to minimize the crossing edge count with nonlinear timing constraints. By using a Lagrangian Approach on Modular Partitioning (LAMP), we merge nonlinear constraints into the objective function. We then decompose the problem into primal and dual subprograms. The primal program is solved by a heuristic Quadratic Boolean Programming approach and the dual program is solved by a subgradient method using a cycle mean method. Experimental results on seven industrial circuits have demonstrated our algorithm is able to achieve an average of 23.25% clock period and latency reductions compared to the best results produced by 20 runs on each test case using a Fiduccia-Mattheyses algorithm. In terms of the average number of crossing edges, our results are only 1.85% more than those of the Fiduccia-Mattheyses algorithm without timing constraints. Compared with previous network flow based approach, our algorithm reduces the average crossing edge count by 14.59%. Furthermore, an average of 7.70% clock period and latency reductions are achieved.